LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY referee IS
	PORT
	(
		reqa, reqb, rela, relb	: IN	STD_LOGIC;
		acka, ackb, sel, cs		: OUT	STD_LOGIC
	);
END referee;

ARCHITECTURE arch_referee OF referee IS
BEGIN
	
	PROCESS(reqa, reqb, rela, relb)
	variable busy: integer := 0;
	BEGIN
		if reqa = '1' and busy = 0 then
			busy := 1;
		end if;
		if reqb = '1' and busy = 0 then
			busy := 2;
		end if;
		if rela = '1' and busy = 1 then
			busy := 0;
		end if;
		if relb = '1' and busy = 2 then
			busy := 0;
		end if;
		
		if busy = 0 then
			sel <= '0';
			cs  <= '0';
		end if;
		
		if busy = 1 then
			sel <= '0';
			cs  <= '1';
			acka <= '1';
			ackb <= '0';
		end if;
		
		if busy = 2 then
			sel <= '1';
			cs  <= '1';
			acka <= '0';
			ackb <='1';
		end if;
	END PROCESS;
END arch_referee;